3 "I.E" PhD positions at Ecole Centrale de Lyon in France

PhD Ferroelectric Transistors (FeFET) Aware Logic Synthesis

. Similar approach will be applied to the design and characterization of logic gates (i.e., NAND, XOR, NOT, …). 3. Characterization of FeFET-based Logic/Memory Elements (M13-M18) • The goal of this task is to

PhD Project DAC Analysis and synthesis of Anomaly Detectors under Critical-time constraints

-time constraint. The critical-time is the maximum time horizon for which a system is considered to be safe after the occurrence of an anomaly, i.e. the system is not in a critical state and is still able

PhD - Towards efficient analysis and synthesis of Heterogeneous Interconnected Systems : application to signal estimation

obtained. This second strategy has recently led to significant results in the special case of homogeneous subsystems, i.e., those represented by the same model (see, for example, [ACPKS23, PKZS23, KSCB16